Job Description
Job Description1. Study Design and define DV Plan for Mentor Review.
2. Base on DV Plan coding Random-Stimulus, Checking Mechanism, Functional Coverage.
3. Run-Simulation then debug and identify fail reason, Fixing DV Environment Problem (Random/Check/Cover).
#LI-YT1Requirement1. 2 Years or Less design verification experience or who interesting with design verification.
2. Familiar Verilog or Systemverilog is required.
3. OOP or UVM is preferred.
2. Base on DV Plan coding Random-Stimulus, Checking Mechanism, Functional Coverage.
3. Run-Simulation then debug and identify fail reason, Fixing DV Environment Problem (Random/Check/Cover).
#LI-YT1Requirement1. 2 Years or Less design verification experience or who interesting with design verification.
2. Familiar Verilog or Systemverilog is required.
3. OOP or UVM is preferred.
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