Job Description

Job Description: Simulation Migration Engineer (SV/UVM)

Experience: 3 to 4 Years

Location: Hyderabad


Key Requirements:

  • Strong hands-on experience in SystemVerilog (SV) and UVM methodology
  • Experience in simulation migration activities, specifically from VCS to Xcelium (Exilium)
  • Good understanding of low power verification concepts
  • Expertise in functional verification , including testbench development and execution
  • Strong skills in coverage analysis (functional & code coverage)
  • Proficient in debugging simulation issues and regression failures
  • Experience in verification environment bring-up and migration support


Interested candidates, kindly share with me your updated profile to .

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