Job Description

5+ years industry experience with below skillset :
  • Strong System Verilog/UVM based verification skills & experience with assertion & coverage-based verification methodology
  • Assertion coding and converging on Formal tools
  • Must have worked on Jasper Gold or VC Formal tools
  • Understanding of common flows, such as Sequential equivalence checks, Register verification using formal is a plus
  • Experience in dynamic verification methodologies will be a plus
  • Experience with scripting languages such as Perl, Python is a plus

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