Job Description

PrincipalStatic Timing Analysis Engineer 
Austin, TX
 

This positioninvolves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems.These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /MLand are specified to exceed best-in-classpower targets. These SoCs deploy a complex, deeply gated clock network with many asynchronous clock sources.
 

Responsibilities 

  • Develop timing constraints at both the IP and SoC level in collaboration with the designers

  • Improve or evolve existing static timinganalysisflows and methodologies.

  • Developrequired timing signoff criteria, such as aging, on chip variation,andsignal integrity

  • Analyze timing reports using scripting techniques to develop insights and drive r...

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