RTL Digital IC Design Engineer: Verify, Synthesize & Debug

Zerro Power Systems Pte Ltd in Singapore is seeking an experienced engineer to design and verify RTL-level digital circuits that meet robust mixed-signal IC design requirements. You'll collaborate with backend teams on synthesis, timing, and perform verification to ensure design correctness.

The ideal candidate will possess a Bachelor’s or Master’s degree in Electronics or Electrical Engineering, along with 2-3 years of relevant experience in digital design validation and strong knowledge of Verilog coding.