UVM Verification Engineer

Role: Verification Engineer

Location: Austin, TX (Onsite)

Duration: 12 months contract

JOB DUTIES:

• Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.

• Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.

• Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-random tests to be run during simulation.

• Be expected to adopt the evolving verification methodologies used in the industry to functionally verify increasingly more complex SoC designs within aggressive, market-driven schedules, and work within the existing verification infrastructure on currently active projects.

• Be familiar with hardware modeling and/or ...