26-049 Cache interference mitigation for RISC-V based architectures

Mission

The need for more performance and, at the same time, less Size, Weight and Power constraints (SWaP) have driven computer architectures to move from monocore designs to multicore ones [1]. As a result, some resources are shared among different cores shared cache, DDR SDRAM), leading to high inter-core interference. This kind of interference may be responsible for high execution time variability, and consequently, be the cause for a loss in execution determinism and performance. This problem has since become a concern in the safety-critical real-time community where assuring a task finishes within its deadlines is imperative. Efforts have been made into it by trying to mitigate their effects, suppress them or make them predictable via software or hardware [2], most of the time at expense of performance. 

Among the resources shared in a multicore platform, the memory hierarchy and especially the shared Last Level Cache (LLC) is a strong source of in...