Job Description
End to end responsible for architecture, feasibility and modelling of ESD solutions needed for IP and SOC. Defining ESD Methodology: Establishing the ESD protection strategy for all silicon developed, including specifying chip and IP level ESD requirements1.Designing ESD Protection Devices: Creating and integrating ESD protection circuits and devices to meet design requirements. This includes designing diodes, grounded gate n-channel MOSFETs, and silicon-controlled rectifiers2.Developing Test Structures: Designing test structures to characterize silicon for ESD and latch-up properties, ensuring the robustness of the ICs against ESD events1.Collaborating with Foundries: Working closely with semiconductor foundries to develop ESD libraries and design rules based on silicon characterization data1.Maintaining ESD Device Libraries: Keeping an updated library of ESD devices to support internal and external design teams1.Conducting ESD Testing and Verification: Generating or reviewing ESD testing plans and ensuring that ICs meet industry standards such as the Human Body Model (HBM) and Charged Device Model (CDM)2.Debugging and Problem-Solving: Leading ESD-related debug activities to identify and resolve issues during the design and manufacturing process1.
Documentation and Reporting: Maintaining detailed records of ESD control measures, test results, and compliance with ESD standards2.Drive culture of innovation to ensure the IP/IC we are doing are best in class benchmarking with competition. Guiding and mentoring the young engineers to develop skills and to acquire critical design competencies.
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