Job Description
We are seeking an Analog IP Modeling Engineer specializing in System Verilog Real Number Modeling (RNM). In this role, you will bridge the gap between analog design and digital verification by creating high-speed, accurate behavioral models (wreal/EE_pkg) for complex analog IPs.
Your work will enable full-chip So C verification by replacing slow SPICE simulations with high-performance event-driven models.
Key Responsibilities:
Model Development: Develop, verify, and maintain System Verilog RNM models for analog IPs (e.g., PLLs, ADCs, DACs, Ser Des, PMIC, and LDOs).
Model Architecture: Define modeling strategies using System Verilog-AMS, wreal, or User Defined Nettypes (UDN) to balance simulation speed and physical accuracy.
Verification & Calibration: Perform model-to-schematic equivalence checking to ensure the behavioral model matches the golden SPICE/Spectre circuit simulations.
Integration: Support So C integration teams by providing models compatible with UVM environments and mixed-signal simulation tools (e.g., Cadence Xcelium/Virtuoso, Siemens Questa ADMS).
Automation: Develop scripts (Python/Perl/Tcl) to automate model generation and verification flows.
Required Skills & Qualifications:
System Verilog Proficiency: Expert knowledge of System Verilog, specifically Real Number Modeling (RNM) and the EE_pkg (IEEE or later).
Analog Knowledge: Strong understanding of analog circuits, including feedback loops, frequency domain analysis, and noise modeling.
EDA Tools: Hands-on experience with mixed-signal simulators such as Cadence Virtuoso/Xcelium (AMS Designer) or Synopsys VCS/Custom Sim
Languages: Proficiency in C/C++, Python, or Verilog-A for auxiliary modeling and automation.
Methodology: Familiarity with UVM (Universal Verification Methodology) as applied to mixed-signal environments.
Preferred Qualifications:
Experience with Event-Driven Analog (EDA) modeling techniques.
Knowledge of signal integrity concepts and high-speed link modeling (e.g., IBIS-AMI).
Degree in Electrical Engineering or a related field with 3+ years of industry experience.
Your work will enable full-chip So C verification by replacing slow SPICE simulations with high-performance event-driven models.
Key Responsibilities:
Model Development: Develop, verify, and maintain System Verilog RNM models for analog IPs (e.g., PLLs, ADCs, DACs, Ser Des, PMIC, and LDOs).
Model Architecture: Define modeling strategies using System Verilog-AMS, wreal, or User Defined Nettypes (UDN) to balance simulation speed and physical accuracy.
Verification & Calibration: Perform model-to-schematic equivalence checking to ensure the behavioral model matches the golden SPICE/Spectre circuit simulations.
Integration: Support So C integration teams by providing models compatible with UVM environments and mixed-signal simulation tools (e.g., Cadence Xcelium/Virtuoso, Siemens Questa ADMS).
Automation: Develop scripts (Python/Perl/Tcl) to automate model generation and verification flows.
Required Skills & Qualifications:
System Verilog Proficiency: Expert knowledge of System Verilog, specifically Real Number Modeling (RNM) and the EE_pkg (IEEE or later).
Analog Knowledge: Strong understanding of analog circuits, including feedback loops, frequency domain analysis, and noise modeling.
EDA Tools: Hands-on experience with mixed-signal simulators such as Cadence Virtuoso/Xcelium (AMS Designer) or Synopsys VCS/Custom Sim
Languages: Proficiency in C/C++, Python, or Verilog-A for auxiliary modeling and automation.
Methodology: Familiarity with UVM (Universal Verification Methodology) as applied to mixed-signal environments.
Preferred Qualifications:
Experience with Event-Driven Analog (EDA) modeling techniques.
Knowledge of signal integrity concepts and high-speed link modeling (e.g., IBIS-AMI).
Degree in Electrical Engineering or a related field with 3+ years of industry experience.
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