Job Description
We are looking for a motivated candidate to work with our Design Verification team. The role involves working on real number modeling and verification of mixed-signal designs using System Verilog and UVM methodologies. This is a hands-on opportunity to gain experience in advanced verification flows and contribute to real-world projects.
Exp: 3+ Years
Location: Bangalore
Notice period: Immediate to 30 days
Key Responsibilities:
Develop and validate real number models (WREAL) for analog/mixed-signal blocks.
Integrate real number models into digital verification environments.
Write and maintain SystemVerilog/UVM testbenches.
Perform functional and regression testing of mixed-signal IPs.
Collaborate with design and verification engineers to debug and resolve issues.
Document modeling and verification strategies and results.
Required Skills:
Good coding skill in Verilog(VAMS) / SV real number models.
Strong understanding of digital and analog design co...
Exp: 3+ Years
Location: Bangalore
Notice period: Immediate to 30 days
Key Responsibilities:
Develop and validate real number models (WREAL) for analog/mixed-signal blocks.
Integrate real number models into digital verification environments.
Write and maintain SystemVerilog/UVM testbenches.
Perform functional and regression testing of mixed-signal IPs.
Collaborate with design and verification engineers to debug and resolve issues.
Document modeling and verification strategies and results.
Required Skills:
Good coding skill in Verilog(VAMS) / SV real number models.
Strong understanding of digital and analog design co...
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