Job Description
Job Title: Analog circuit Design Engineer
Location: Bangalore, Hyderabad, India
Experience Levels & Openings:
Senior Level: 15–18 years
Mid Level: 3–5 years
About the Project:
The team will work on end-to-end analog design, including simulations, circuit design, verification, and layout back-annotation.
The primary focus is on high-speed I/O (Input/Output) circuits
Key Responsibilities:
Perform analog circuit design for high-speed I/O blocks
Execute design simulations, including regression and Monte Carlo analysis
Collaborate with teams for design reviews and system-level verification
Work on design changes and ensure compliance with specifications
Handle layout back-annotation and parasitic extraction for nanometer nodes
Participate in manufacturing process evaluation and tape-out readiness
Ensure familiarity with PDKs and process limitations for nanometer technologies
Required Skills & Expertise:
Strong experience in High-Speed I/O analog design
Hands-on experience with nanometer technologies (3–4 years for senior roles)
Proficiency in regression simulations, Monte Carlo analysis, and analog verification
Experience with industry-standard EDA tools
Ability to work independently and take ownership of design blocks
Additional Information:
Project design changes aligned with TSMC processes (critical for approvals)
Preference for Bangalore-based candidates for face-to-face interviews
Remote interviews may be considered for Hyderabad candidates after initial screening
Location: Bangalore, Hyderabad, India
Experience Levels & Openings:
Senior Level: 15–18 years
Mid Level: 3–5 years
About the Project:
The team will work on end-to-end analog design, including simulations, circuit design, verification, and layout back-annotation.
The primary focus is on high-speed I/O (Input/Output) circuits
Key Responsibilities:
Perform analog circuit design for high-speed I/O blocks
Execute design simulations, including regression and Monte Carlo analysis
Collaborate with teams for design reviews and system-level verification
Work on design changes and ensure compliance with specifications
Handle layout back-annotation and parasitic extraction for nanometer nodes
Participate in manufacturing process evaluation and tape-out readiness
Ensure familiarity with PDKs and process limitations for nanometer technologies
Required Skills & Expertise:
Strong experience in High-Speed I/O analog design
Hands-on experience with nanometer technologies (3–4 years for senior roles)
Proficiency in regression simulations, Monte Carlo analysis, and analog verification
Experience with industry-standard EDA tools
Ability to work independently and take ownership of design blocks
Additional Information:
Project design changes aligned with TSMC processes (critical for approvals)
Preference for Bangalore-based candidates for face-to-face interviews
Remote interviews may be considered for Hyderabad candidates after initial screening
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