Job Description
Title: Analog Layout Design Engineer
Experience:4-7 years
Location: Hyderabad
Job Description
We are seeking an experienced Analog Layout Design Engineer to work on cutting-edge TSMC advanced technology nodes (≤16nm, 12nm, 7nm, 5nm, 3nm) . The role involves full-cycle custom layout of high-performance analog and mixed-signal IPs, with strong emphasis on layout quality, reliability, and silicon success.
Key Responsibilities
Perform full-custom analog and mixed-signal layout for blocks such as:
PLL, ADC/DAC, LDO, Bandgap, SerDes, high-speed I/O, memory peripherals
Work extensively on TSMC lower/advanced nodes (16nm FinFET and below)
Apply advanced matching techniques (common-centroid, inter-digitization, symmetry)
Handle device placement, routing, shielding, and EM/IR-aware layout
Run and debug DRC, LVS, ERC, ANT, DFM, and reliability checks
Address FinFET-specific layout constraints (quantization, orientation, poly rules)
Collaborate c...
Experience:4-7 years
Location: Hyderabad
Job Description
We are seeking an experienced Analog Layout Design Engineer to work on cutting-edge TSMC advanced technology nodes (≤16nm, 12nm, 7nm, 5nm, 3nm) . The role involves full-cycle custom layout of high-performance analog and mixed-signal IPs, with strong emphasis on layout quality, reliability, and silicon success.
Key Responsibilities
Perform full-custom analog and mixed-signal layout for blocks such as:
PLL, ADC/DAC, LDO, Bandgap, SerDes, high-speed I/O, memory peripherals
Work extensively on TSMC lower/advanced nodes (16nm FinFET and below)
Apply advanced matching techniques (common-centroid, inter-digitization, symmetry)
Handle device placement, routing, shielding, and EM/IR-aware layout
Run and debug DRC, LVS, ERC, ANT, DFM, and reliability checks
Address FinFET-specific layout constraints (quantization, orientation, poly rules)
Collaborate c...
Apply for this Position
Ready to join SysTechCorp Inc? Click the button below to submit your application.
Submit Application