Analog layout design,Staff Engineer

• Hands-on development of layout for next-generation DDR/HBM/UCIe IPs.
• Solving complex problems and debugging issues effectively.
• Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements.
• Ensuring compliance with DRC, LVS, ERC, and antenna rules.
• Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below).
• Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation.

The Impact You Will Have:

• Enhancing the performance and reliability of Synopsys' DDR/HBM/UCIe IPs.
• Accelerating the integration of advanced capabilities into SoCs.
• Reducing risk and improving time-to-market for differentiated products.
• Driving innovation in semiconductor technology and design.
• Contributing to the success of Synopsys' Silicon IP business.
• Fostering a collaborative and i...