Job Description

Role - RTL Design Engineer

Experience - 5years-10years

NP - Immediate to 60Days

Location - Pan India

JD of Senior ASIC/SoC RTL Engineer/Lead

  • Expertise in SoC subsystem/IP design
  • Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
  • In depth knowledge on RTL quality checks (Lint, CDC)
  • Knowledge of synthesis and low power is a plus
  • Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
  • Good understanding of timing concepts
  • Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI
  • Expertise in setting up and using tools like a. Spyglass Lint/CDC b. Synopsys DC c. Verdi/Xcellium
  • Understanding of scripting languages like Make flow, Perl ,shell, python etc
  • Understanding of processor architecture and/or ARM debug architecture is a plus
  • Able to help and debug issues for mu...

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