ASIC Engineer Intern, Design Verification

**Summary:**

Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our services are delivered. By holding this role, you will be an integral member of an ASIC team to build accelerators for some of our top workloads enabling our data centers to scale efficiently. You will have an opportunity to participate in design and verification of advanced IPs using state of the art tools. Come work and learn alongside our ASIC engineers to build “Green” data center accelerators.Internships are twelve (12) to sixteen (16) weeks long.

**Required Skills:**

ASIC Engineer Intern, Design Verification Responsibilities:

1. Develop tests, checkers and coverage to help verify designs

2. Develop understanding of the architecture and microarchitecture of designs

3. SystemVerilog/UVM/C code to generate test content

4. Develop scripts to automate various processes

5. Debug test failures, work with design, verification and modeling teams to fix and verify the fixes

6. Help improve verification processes and contribute to methodology

**Minimum Qualifications:**

Minimum Qualifications:

7. Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields

8. Knowledge of Computer Architecture and Logic Design fundamentals

9. Experience thinking critically and creatively on how to verify designs, solve problems

10. Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment

11. Intent to return to degree-program after the completion of the internship/co-op

**Preferred Qualifications:**

Preferred Qualifications:

12. Currently has, or is in the process of obtaining, a Masters or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields

13. Knowledge of SystemVerilog/VHDL/Verilog

14. Scripting with Python or perl

**Industry:** Internet