ASIC RTL Design Engineer

We are seeking a hands-on RTL Design Engineer to develop ASIC RTL blocks and algorithms with strong attention to design quality and correctness. This role emphasizes coding, verification, and quality checks at the block level.

Job Description:

• Develop RTL blocks and algorithms using Verilog/SystemVerilog for ASIC designs
• Run quality checks including CDC, Lint, and X-propagation, and clean up design issues
• Apply knowledge of synthesis flows and constraint writing (good to have)
• Ensure design correctness and adherence to coding standards
• Participate in design reviews and debug RTL issues
• Collaborate with cross-functional teams to maintain high-quality RTL delivery

If you’re looking to contribute to high-quality RTL blocks and take ownership of block-level ASIC designs, this role offers strong technical growth and impact.

Thanks,

Karthik Kumar