Job Description
Proxelera is a fast-growing, 4-year-old semiconductor and high-tech engineering company, delivering cutting-edge solutions across architecture, design, verification, and analytics. We work on globally recognized projects with leading customers across US & APAC. We are currently hiring immediate VLSI experts for our client, ODC and Turnkey projects.
Job Title: ASIC RTL Design Engineer
Experience: 4–6 Years | Location: Bangalore (Proxelera Office)
Job Description
- Strong RTL coding in Verilog/System Verilog is non-negotiable, this is a pure RTL design role.
- Own block-level RTL development from micro-architecture to clean, synthesizable RTL.
- Design FSM/FSMD, apply pipelining, and optimize RTL for timing and performance.
- Hands-on execution and closure of Lint, CDC, X-prop, and structural checks.
- Debug RTL vs synthesis mismatches and functional issues.
- Work closely with DV teams to resolve design bugs efficiently.
- Solid understanding of logic synthesis and constraint intent at block/top level.
- Support timing closure in collaboration with PD and STA teams.
- Exposure to pipelined processor architectures (ARM or RISC-V preferred).
- Maintain clear documentation of RTL changes and design decisions.
Apply:
Referrals welcome — your recommendation could be our next star hire!
Job Title: ASIC RTL Design Engineer
Experience: 4–6 Years | Location: Bangalore (Proxelera Office)
Job Description
- Strong RTL coding in Verilog/System Verilog is non-negotiable, this is a pure RTL design role.
- Own block-level RTL development from micro-architecture to clean, synthesizable RTL.
- Design FSM/FSMD, apply pipelining, and optimize RTL for timing and performance.
- Hands-on execution and closure of Lint, CDC, X-prop, and structural checks.
- Debug RTL vs synthesis mismatches and functional issues.
- Work closely with DV teams to resolve design bugs efficiently.
- Solid understanding of logic synthesis and constraint intent at block/top level.
- Support timing closure in collaboration with PD and STA teams.
- Exposure to pipelined processor architectures (ARM or RISC-V preferred).
- Maintain clear documentation of RTL changes and design decisions.
Apply:
Referrals welcome — your recommendation could be our next star hire!
Apply for this Position
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