Asic rtl design engineer (soc/subsystem)

We are hiring a Senior / Principal ASIC RTL Design Engineer to take full ownership of complex So C or large subsystem RTL, driving designs from micro-architecture through tapeout and silicon bring-up. This role demands strong hands-on RTL expertise and deep collaboration across design, PD, and validation teams.
Job Description:
- Own end-to-end RTL development for So C-level or large subsystem blocks, from micro-architecture definition to tapeout and bring-up
- Develop high-quality synthesizable System Verilog / Verilog RTL, including clock/reset architecture and low-power design techniques (UPF, isolation, retention)
- Lead block and subsystem integration, and work closely with synthesis and Pn R teams on timing, power, area, DFT hooks, and ECOs
- Drive design reviews, debug RTL issues, and support silicon validation and post-silicon debug activities
- Collaborate with DV teams on test planning, assertions, and coverage; support emulation.
- Apply hands-on experience across AMBA protocols (AXI/ACE/AHB/APB), with exposure to subsystems such as interconnects, memory, high-speed I/O, security, or power domains; scripting (Tcl/Python) for productivity is a plus
If you’re looking for true ownership of silicon-critical RTL and the opportunity to influence real So C designs from concept to silicon, this role offers strong technical depth and impact.
Regards,
Karthik Kumar