Job Description

Required Skills:
- 5+ years in RTL design or verification (2+ years formal)
- Knowledge of System Verilog, SVA/PSL, assertions
- Experience with Jasper Gold, One Spin, or VC Formal
- Familiarity with AI/ML in EDA tools
- Hands-on with Jasper Golds Smart Proof, Visualize TM, Quiet Trac...

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