Job Description
Required Skills:
- 5+ years in RTL design or verification (2+ years formal)
- Knowledge of SystemVerilog, SVA/PSL, assertions
- Experience with JasperGold, OneSpin, or VC Formal
- Familiarity with AI/ML in EDA tools
- Hands-on with JasperGolds Smart Proof, VisualizeTM, QuietTraceTM
- 5+ years in RTL design or verification (2+ years formal)
- Knowledge of SystemVerilog, SVA/PSL, assertions
- Experience with JasperGold, OneSpin, or VC Formal
- Familiarity with AI/ML in EDA tools
- Hands-on with JasperGolds Smart Proof, VisualizeTM, QuietTraceTM
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