Asic Verification Lead

Description:We are seeking an experienced Senior Verification Engineer with 8+ years of industry expertise indigital design verification. The ideal candidate will have a strong background in SystemVerilog andUVM, with proven experience in block-level, subsystem, and top-level verification. Knowledge ofboth formal and dynamic verification methodologies is essential.

In this role, you will work within the Verification Team to ensure the correctness andfunctionality of complex microprocessor architectures at the RTL level. You will develop and applyadvanced verification methodologies, build testbenches, run simulations, and collaborate closelywith design teams to deliver high-quality, production-ready designs.

Requirements:

• Master's or PhD in Computer Science, Electrical Engineering, or a related field
• Proficiency in SystemVerilog and UVM
• Strong scripting skills (Python, Perl, Bash, Tcl)
• 8+ years of relevant industry experience
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