Job Description
Job Description- Responsible for leading a team of STA engineers and close high frequency, low power, multi-hierarchy ARM based CPU and MCU Design.
- Work with Physical Design to close on Place & Route related timing issues, Analysis of timing from synthesis to verify constraints.
- Work with Architects and logic designers to generate and verify timing constraints.
- Derive STA Signoff corners and PVT to achieve best possible silicon yield and aging requirement.
#LI-WC1
Requirement- Good Knowledge of ARM CPU Architecture and Design.
- > 10 years of STA experiences, expertise in DVFS, advanced tech node, <4nm, STA Signoff methodology.
- Passionate about Optimizing Power, Performance and Area of newest ARM CPU.
- Work with Physical Design to close on Place & Route related timing issues, Analysis of timing from synthesis to verify constraints.
- Work with Architects and logic designers to generate and verify timing constraints.
- Derive STA Signoff corners and PVT to achieve best possible silicon yield and aging requirement.
#LI-WC1
Requirement- Good Knowledge of ARM CPU Architecture and Design.
- > 10 years of STA experiences, expertise in DVFS, advanced tech node, <4nm, STA Signoff methodology.
- Passionate about Optimizing Power, Performance and Area of newest ARM CPU.
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