DDR verification engineer

DDR Verification engineer

Job Description: DDR and SOC verification engineer

Experience: 4 to 9

Location: Bangalore

NP should be Max 0-30 days

Qualifications: B.Tech/B.E/M.Tech/M.E

Role and Responsibilities: Responsible for DDR PHY verification at SoC level Execute Gate level simulations.

Responsible for code coverage closure

Skill Requirements: Hands on experience in SV/UVM based testbench development. Good understanding of DDR protocol system level scenarios in SOC DDR model integration into SOC, JEDEC spec understanding Basic knowledge in Bus protocols-APB, AHB, AXI Experience in debugging gate level simulations, low power simulations

Good to have: Scripting knowledge in Python/Perl.

Interested candidates can share resume to