Design and verification

Greetings from ACL Digital! We are expanding our Design & Verification teams and looking for skilled professionals across multiple DV roles.
Interested candidates can apply or refer friends by sharing resumes to — referrals are most welcome.
JD 1 – Formal Verification Engineer
• 4–13 years of Formal Verification experience
• IP & So C-level formal verification exposure
• Low-speed peripherals: I2 C, SPI, UART, GPIO
• Strong in properties, assertions & proofs
Location: Bangalore | NP: 30 Days
JD 2 – Principal / Lead Design Verification Engineer
• 15+ years of DV experience in IP & So C verification
• Strong Verilog, System Verilog & UVM expertise
• Own end-to-end DV: test planning, execution, debug & sign-off
• Lead and mentor senior DV teams
Location: Bangalore | NP: 30 Days
JD 3 – Senior Design Verification Engineer (Cloud / Google)
• 8+ years of DV experience
• Strong IP & So C verification using SV/UVM
• Excellent debug, coverage and regression ownership
• Hands-on experience with Verilog
Location: Bangalore | NP: 30 Days
JD 4 – Pre-Silicon / Firmware Verification Engineer
• 5–12 years of pre-silicon verification experience
• Boot code & firmware verification using So C C-based flows
• SV/UVM for functional or mixed-signal DV
• Protocols: SPI, I2 C, CSI2, LVDS, CPU verification
Location: Bangalore | NP: 30 Days
JD 5 – AMS Verification Lead
• 12+ years of AMS verification experience
• Ground-up AMS SV/UVM environment development
• Ser Des experience: PCIe / USB3 / MIPI
• Lead AMS DV from test planning to sign-off
Location: Bangalore | NP: 30 Days
JD 6 – So C Design Verification Engineer
• 5+ years of Design Verification experience
• Strong So C-level verification exposure
• C language mandatory for So C verification
• SV & UVM experience required
Location: Bangalore | NP: 30 Days
JD 7 – Senior DV Engineer – Low Power
• 8–10 years of DV experience
• IP, Subsystem & So C verification expertise
• Strong UPF-based low-power verification
• Excellent trace, debug & regression skills
Location: Bangalore | NP: 30 Days
JD 8 – DV Engineer – Power Aware Verification
• 8–12 years of DV experience
• SV/UVM-based verification mandatory
• UPF-based low-power & power-aware simulations
• Trace and debug experience at IP/SS/So C level
Location: Bangalore | NP: 30 Days
JD 9 – DV Engineer – Specman
• 8–15 years of Design Verification experience
• Strong SV/UVM-based verification
• Specman/e experience is mandatory
• Mixed-language testbench exposure preferred
Location: Bangalore | NP: 30 Days
JD 10 – Processor So C DV Lead & Engineers
Lead: 15+ years | Engineers: 3–10 years
• Processor-based So C verification experience
• ARM Cortex-M/A, AMBA (AXI/AHB) expertise
• C/Assembly testcase development
• Lead to manage 10+ DV engineers
Location: Bangalore | NP: 30 Days