Job Description
JD 1: RTL Design Engineer – AI
Experience: As per project need
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong RTL design using Verilog / SystemVerilog
- Experience in AI/ML accelerator hardware
- Design of MAC arrays, pipelines, datapath & control logic
- Knowledge of systolic / vector / tensor architectures
- Experience with AXI / AHB interfaces
- Hands-on with RTL simulation & debug (VCS / Questa / Xcelium)
JD 2: VCLP / Low Power Implementation Engineer
Experience: 4 – 13 Years
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong expertise in UPF (IEEE 1801)
- Hands-on low power implementation for multi-voltage SoCs
- Experience with power domains, i...
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