Design engineer

JD 1: RTL Design Engineer – AI
Experience: As per project need
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong RTL design using Verilog / System Verilog
- Experience in AI/ML accelerator hardware
- Design of MAC arrays, pipelines, datapath & control logic
- Knowledge of systolic / vector / tensor architectures
- Experience with AXI / AHB interfaces
- Hands-on with RTL simulation & debug (VCS / Questa / Xcelium)
JD 2: VCLP / Low Power Implementation Engineer
Experience: 4 – 13 Years
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong expertise in UPF (IEEE 1801)
- Hands-on low power implementation for multi-voltage So Cs
- Experience with power domains, isolation, level shifters, retention
- Knowledge of power gating & clock gating
- Low power debug using power-aware simulation
- Experience with Synopsys / Cadence low power flows
JD 3: ASIC Micro-Architecture Engineer – Automotive
Experience: 5 – 14 Years
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong ASIC / So C micro-architecture experience
- Hands-on automotive project experience (ISO 26262 / ASIL)
- Architecture definition & RTL handoff
- Knowledge of AMBA protocols (AXI / AHB / APB)
- Experience with safety mechanisms (ECC, redundancy, fault handling)
- Ability to write architecture & design specifications
Interested candidates can share their resume to:
About ALTEN Calsoft:
ALTEN Calsoft Labs is part of the ALTEN Group, a global engineering and technology consulting leader. We specialize in semiconductor, embedded, and digital engineering solutions for global customers across automotive, telecom, and high-tech domains.