Job Description
JD 1: RTL Design Engineer – AI
Experience: As per project need
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong RTL design using Verilog / System Verilog
- Experience in AI/ML accelerator hardware
- Design of MAC arrays, pipelines, datapath & control logic
...
Experience: As per project need
Location: Bangalore | Notice Period: 30 days
Required Skills:
- Strong RTL design using Verilog / System Verilog
- Experience in AI/ML accelerator hardware
- Design of MAC arrays, pipelines, datapath & control logic
...
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