Job Description
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
+ STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs
+ Timing analysis, validation and debug across multiple PVT conditions
+ Run Tempus for STA flow optimization and Spice to STA correlation.
+ Required Skills -
+ Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years experience
+ Physical design experience in ASIC design environment
+ Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
+ Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
+ Hands-on experience with STA tools - Prime-time, Tempus
+ Have experience working on timing convergence at Chip-level and Hard-Macro level.
+ In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
+ A strong grasp of ML fundamentals
+ Should have excellent leadership, communication, analytical and problem solving skills
+ Should be self-motivated and good team player
+ Evaluate multiple timing methodologies/tools on different designs and technology nodes
+ Work closely with RnD to explore Agentic AI capabilities to improve design efficiency.
+ Development, automation and maintenance of EDA flows and scripts for physical implementation
+ Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
+ Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
+ Solid scripting skills including Python and Tcl.
We’re doing work that matters. Help us solve what others can’t.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs)
Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization.
+ Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/equal-employment-opportunity-policy.pdf)
We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected].
Privacy Policy:
Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html) .
E-Verify Cadence participates in the
E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
+ STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs
+ Timing analysis, validation and debug across multiple PVT conditions
+ Run Tempus for STA flow optimization and Spice to STA correlation.
+ Required Skills -
+ Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes with 2 + years experience
+ Physical design experience in ASIC design environment
+ Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification
+ Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling.
+ Hands-on experience with STA tools - Prime-time, Tempus
+ Have experience working on timing convergence at Chip-level and Hard-Macro level.
+ In-depth knowledge crosstalk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling.
+ A strong grasp of ML fundamentals
+ Should have excellent leadership, communication, analytical and problem solving skills
+ Should be self-motivated and good team player
+ Evaluate multiple timing methodologies/tools on different designs and technology nodes
+ Work closely with RnD to explore Agentic AI capabilities to improve design efficiency.
+ Development, automation and maintenance of EDA flows and scripts for physical implementation
+ Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs.
+ Digital design implementation using Cadence EDA tools - Genus, Innovus, Conformal, Litmus, Tempus, Voltus, Certus, Pegasus and other backend tools
+ Solid scripting skills including Python and Tcl.
We’re doing work that matters. Help us solve what others can’t.
Additional Jobs (https://cadence.wd1.myworkdayjobs.com/addl\_jobs)
Equal Employment Opportunity Policy:
Cadence is committed to equal employment opportunity throughout all levels of the organization.
+ Read the policy(opens in a new tab) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/equal-employment-opportunity-policy.pdf)
We welcome your interest in the company and want to make sure our job site is accessible to all. If you experience difficulty using this site or to request a reasonable accommodation, please contact [email protected].
Privacy Policy:
Job Applicant If you are a job seeker creating a profile using our careers website, please see the privacy policy(opens in a new tab) (https://www.cadence.com/en\_US/home/privacy/privacy-policy.html) .
E-Verify Cadence participates in the
E-Verify program in certain U.S. locations as required by law. Download More Information on E-Verify (64K) (https://www.cadence.com/content/dam/cadence-www/global/en\_US/documents/company/careers/e-verify-participation-poster.pdf)
Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.
Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.
Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.
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