Design Engineering Architech

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL

- Design and implement RTL for DFT IP incl. POST, IST

- Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification

- Own and maintain, extend, and enhance existing DFT IP like LBIST

We’re doing work that matters. Help us solve what others can’t.