Job Description
Experience: 5 Years
Location: Bangalore/Hyderabad
Education: B. E/B. Tech in ECE/EEE or M. E/M. Tech in VLSI/Electronics
Roles and Responsibilities
DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols.
Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using System Verilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.
Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management.
Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol va...
Location: Bangalore/Hyderabad
Education: B. E/B. Tech in ECE/EEE or M. E/M. Tech in VLSI/Electronics
Roles and Responsibilities
DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3, DDR4, DDR5, and other memory interface protocols.
Testbench Development: Develop and implement scalable, reusable, and efficient verification environments and testbenches for DDR designs using System Verilog, UVM (Universal Verification Methodology), and other industry-standard verification methodologies.
Protocol Compliance: Ensure the DDR design meets protocol specifications, including command, data, and clock synchronization, read/write cycles, burst transfers, refresh cycles, error handling, and power management.
Verification Plan Creation: Develop detailed verification plans based on DDR specifications and requirements, ensuring full coverage of corner cases, timing, and protocol va...
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