Job Description
Job Title: Design Verification Engineer
Experience: 4+ years
Strong Experience in IP/Sub System verification
Strong working knowledge of any one protocol Ethernet, MIPI, WIFI, PCIe, CXL, DDR, AMBA: AXI, AHB, NOC
Excellent in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development (BFM, Scoreboard, Checkers, Monitors), assertions, testbenches, test plans, and coverage & assertions
Excellent debugging skills
Experience: 4+ years
Strong Experience in IP/Sub System verification
Strong working knowledge of any one protocol Ethernet, MIPI, WIFI, PCIe, CXL, DDR, AMBA: AXI, AHB, NOC
Excellent in System Verilog (SV), Universal Verification Methodology (UVM), test bench component development (BFM, Scoreboard, Checkers, Monitors), assertions, testbenches, test plans, and coverage & assertions
Excellent debugging skills
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