Job Description
Design Verification | 5 To 16 years | Bangalore
Responsibilities:
- Perform IP/So C DV and CPU DV for complex architectures.
- Develop scalable test benches (BFM, Scoreboard, Checkers, Monitors) in System Verilog and UVM.
- Create tests, functional coverage models, and System Verilog assertions.
- Debug issues related to memory architecture (DRAM, Cache, MMU), AXI, PCIe, DDR/HBM.
- Collaborate with design teams to ensure verification completeness.
Technical Skills:
- Excellent in System Verilog (SV) and UVM.
- Strong knowledge of AMBA protocols, ARM v8/v9, RISC-V, x86 architecture.
- Proficient in OOP/C++, Python scripting.
- Excellent debugging skills.
Responsibilities:
- Perform IP/So C DV and CPU DV for complex architectures.
- Develop scalable test benches (BFM, Scoreboard, Checkers, Monitors) in System Verilog and UVM.
- Create tests, functional coverage models, and System Verilog assertions.
- Debug issues related to memory architecture (DRAM, Cache, MMU), AXI, PCIe, DDR/HBM.
- Collaborate with design teams to ensure verification completeness.
Technical Skills:
- Excellent in System Verilog (SV) and UVM.
- Strong knowledge of AMBA protocols, ARM v8/v9, RISC-V, x86 architecture.
- Proficient in OOP/C++, Python scripting.
- Excellent debugging skills.
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