Job Description
Position: Design Verification Engineer (IP / So C / Low-Power So C)
Experience: 5 to 10 years
Location: Bengaluru
Job Description:
We are looking for experienced Design Verification Engineers to work on complex IPs, So Cs, and low-power So C designs. The role involves hands-on verification, testbench development, coverage closure, and debugging of advanced semiconductor designs.
Key Responsibilities:
Perform functional verification of IPs, So Cs, or sub-systems using System Verilog and UVM
Develop verification testbenches from scratch or build major TB components such as drivers, sequencers, monitors, agents, scoreboards, and checkers
Create detailed testplans from design specifications and ensure complete feature coverage
Execute functional and code coverage, identify coverage gaps, and write directed and constrained-random tests
Debug complex issues using waveform analysis and simulation tools
Work closely with design, architecture, and validation teams to resolve verification issues
Required Skills & Experience:
5–10 years of hands-on Design Verification experience in IP-level or So C-level verification
Strong experience in System Verilog and UVM methodology
Experience verifying industry-standard protocols such as PCIe, AXI, CHI, or UCIe
Excellent debugging skills using tools like Verdi, Verisium, or Sim Vision
Experience in coverage-driven verification and closure
Experience: 5 to 10 years
Location: Bengaluru
Job Description:
We are looking for experienced Design Verification Engineers to work on complex IPs, So Cs, and low-power So C designs. The role involves hands-on verification, testbench development, coverage closure, and debugging of advanced semiconductor designs.
Key Responsibilities:
Perform functional verification of IPs, So Cs, or sub-systems using System Verilog and UVM
Develop verification testbenches from scratch or build major TB components such as drivers, sequencers, monitors, agents, scoreboards, and checkers
Create detailed testplans from design specifications and ensure complete feature coverage
Execute functional and code coverage, identify coverage gaps, and write directed and constrained-random tests
Debug complex issues using waveform analysis and simulation tools
Work closely with design, architecture, and validation teams to resolve verification issues
Required Skills & Experience:
5–10 years of hands-on Design Verification experience in IP-level or So C-level verification
Strong experience in System Verilog and UVM methodology
Experience verifying industry-standard protocols such as PCIe, AXI, CHI, or UCIe
Excellent debugging skills using tools like Verdi, Verisium, or Sim Vision
Experience in coverage-driven verification and closure
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