Job Description
We are seeking a skilled and motivated Design Verification Engineer (DV) with expertise in Ethernet protocols, MAC layer functionality, and Ro CE (RDMA over Converged Ethernet). The ideal candidate will have hands-on experience with Synopsys Ethernet PHY and controller IPs , and a strong understanding of high-performance networking technologies.
Key Responsibilities
Develop and execute verification plans for Ethernet MAC and PHY IP blocks
Design and implement testbenches using industry-standard methodologies (UVM, System Verilog)
Validate Ro CE protocol implementations for low-latency, high-throughput data transfer
Collaborate with design and architecture teams to ensure functional correctness and performance
Debug and resolve issues across simulation and emulation platforms
Contribute to coverage analysis and closure
Preferred Qualifications
Strong knowledge of Ethernet protocols , including MAC layer operations Experience with Ro CE (RDMA over Co...
Key Responsibilities
Develop and execute verification plans for Ethernet MAC and PHY IP blocks
Design and implement testbenches using industry-standard methodologies (UVM, System Verilog)
Validate Ro CE protocol implementations for low-latency, high-throughput data transfer
Collaborate with design and architecture teams to ensure functional correctness and performance
Debug and resolve issues across simulation and emulation platforms
Contribute to coverage analysis and closure
Preferred Qualifications
Strong knowledge of Ethernet protocols , including MAC layer operations Experience with Ro CE (RDMA over Co...
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