Design Verification Engineer

Title: Sr. Design Verification Engineer

Type: Contract

Duration: up to 12 months (maybe longer)

Location: Remote

We are seeking a highly skilled Senior ASIC Design Verification Engineer to lead and execute verification of high-performance UCIe (Universal Chiplet Interconnect Express) IP and advanced SoC subsystems. This role focuses on developing scalable, coverage-driven verification environments for next-generation chiplet-based architectures used in AI, HPC, networking, and automotive applications.

You will work closely with architecture, design, and physical implementation teams to ensure functional correctness, protocol compliance, and high-quality silicon delivery.

Key Responsibilities

• Lead functional verification of UCIe IP and subsystems from specification through silicon validation.
• Develop and maintain SystemVerilog / UVM-based verification environments .
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