Job Description

What you will do

  • Architect DFT solutions for SOCs with multiple sub-blocks/partitions and complex soft/hard IPs with complex DFT requirements
  • Coordinate/Negotiate DFT requirements with the project teams and the customers
  • Implement, and validate innovative DFT techniques on SOCs and sub-systems.
  • Define timing constraints for DFT test-modes
  • Insert boundary scan, compression, MBIST/R(epair), OPCG (OCC) for large-scale low-power designs in advanced nodes (7nm and beyond)
  • Generate test patterns, debug/improve fault coverage, support debug of post-silicon test patterns, diagnose memory and scan issues
  • Work closely with the physical design team in the context of timing violations, signal/power integrity issues, routing congestion, etc.
  • Work closely with the test engineering team on silicon characterization and validation

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