DFT Engineer

Hiring: DFT Engineers

Experience: 5 – 25 Years | Location: Bangalore / Hyderabad / Ahmedabad

We are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether you are a hands-on technical lead or an industry veteran with architectural expertise, we have a role that will challenge and grow your skills in advanced silicon testing.

## Core Responsibilities

You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery. Key focus areas include:

• Scan Architecture & Implementation: Implementation of Scan insertion at both RTL and Gate levels, including EDT/OCC.
• Block level ATPG & Coverage: Execution of Block-level ATPG, comprehensive DRC analysis, and coverage optimization.
• Verification: Handling Pattern simulations (both Timing and Non-timing).
• SOC Integration: Pattern Retargeting to SOC/Subsystem levels and performing full-chip simulations.
• Memory & IP Test: Integration and simulation of MBIST, IJTAG, and Boundary Scan (JTAG) .
• Debug & Analysis: Independent debugging of DFT simulations and netlist handling.

### Technical Requirements

Must-Have Skills:

• Netlist Management: Handling of netlists and ATPG simulations.
• Pattern Retargeting: Proven experience in retargeting block-level patterns to top-level and subsequent simulation debug.
• Standards: Deep understanding of ICL/PDL.
• Tools: Handling of at least one major tool suite:
• Siemens (Tessent)
• Synopsys (TestMAX / TetraMAX)
• Cadence (Modus)

Preferred & Advanced Skills:

• Experience with SSN .
• Knowledge of Analog DFT methodologies.
• Proficiency in SpyGlass for DFT linting and early analysis. Handling of RTL level DFT.

### What We Are Looking For

• Mid-Level (5-10 Years): Strong execution focus, ability to own blocks independently, and proficiency in simulation debug.
• Senior/Principal (10-25 Years): Ability to define DFT strategy, architect SOC-level test solutions, mentor junior engineers, and interface with design/foundry teams.