Job Description
Job Title: DFT Engineer
Experience Level: 2+ years
Location: Hyderabad and Banglaore
Job Description:
Key Responsibilities:
- Develop and implement DFT architecture and methodologies for ASIC/SoC designs.
- Insert and verify scan chains (scan insertion, ATPG, scan stitching).
- Implement MBIST/Logic BIST using industry-standard tools and flows.
- Work on boundary scan (IEEE 1149.1), JTAG implementation and validation.
- Create and validate test patterns (ATPG) for stuck-at, transition faults, and path delay faults.
- Work with RTL, synthesis, and physical design teams to ensure DFT compliance.
- Perform fault simulations, coverage analysis, and debug test pattern issues.
- Support silicon bring-up, ATE test development, and yield enhancement.
- Deliver final test models and documentation for production testing.
Required Skills and Experience:
- B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Design.
- 4+ years of hands-on experience in DFT for complex ASIC or SoC projects.
- Strong knowledge of scan insertion, ATPG, MBIST, and boundary scan techniques.
- Experience with industry tools such as:
- DFT Tools: Synopsys DFT Compiler, Tetramax, TetraMAX II, Siemens Tessent
- MBIST Tools: Synopsys TestMAX/DFTMAX, Tessent MBIST
- Simulation/Debug: Verilog/VHDL, ModelSim, VCS, or Questa
- Understanding of STA and timing constraints related to DFT insertion.
- Familiarity with scripting languages like Python, Perl, or Tcl.
- Solid understanding of digital design concepts and RTL design.
Preferred Qualifications:
- Exposure to ATE (Automatic Test Equipment) patterns and test flow development.
- Experience in hierarchical DFT, RTL-level DFT insertion, and low-power DFT design.
- Knowledge of IEEE standards (1149.1, 1500, 1687).
- Good communication, teamwork, and problem-solving skills.
Why Join Us?
- Work on cutting-edge DFT for advanced semiconductor nodes.
- Join a dynamic team in a fast-paced, innovation-driven environment.
- Competitive compensation and opportunities for career growth.
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