Job Description

We are looking for a DFT Engineer with solid domain expertise to support DFT implementation and validation across IP and SoC levels. This role focuses on scan methodologies, test coverage, and robust design-for-test practices.


Job Description:

  • Work within the DFT domain to implement and validate structural DFT solutions.
  • Apply strong understanding of digital design concepts using VHDL/Verilog.
  • Implement scan compression at IP level and support scan retargeting at SoC level.
  • Utilize DFT tools such as TestKompress, Tessent Diagnosis, MBIST, and simulation tools.
  • Apply knowledge of VLSI testing, fault models, and DFT methodologies.
  • Leverage exposure to FPGA and Perl/Shell scripting as a value add.


If you’re looking to strengthen testability and quality of silicon designs through hands-on DFT ownership, this role offers focused technical depth and impact.


Thanks,

Karthik Kumar

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