Job Description

Job DescriptionJob Description
As a member of DFT engineering team, the candidate will develop methodologies and implement DFT for pre/post-silicon DFT flow and contribute to SOC/Automotive/RISC-V product test quality.
Work with senior engineers across disciplines (DE, IMP, PE, TE) to meet low cost and high quality DFT deliverables.
RequirementRequirement:
(Exp.- 7-12 Years)

Detailed knowledge of Design for Testability and IC Design Flow.

Hands-on experience in post-silicon debug, ATE bring-up, low-power DFT methodologies, DFT architecture and sound understanding of DFT clocking strategies

Experience with tools (Synopsys/Siemens) and methodologies for DFT

Experience with Automotive Low DPPM DFT / LBIST /IST

Hierarchical DFT, LBIST, MBIST, Diagnosis flows

Strong DFT SCAN implementation skills, top DFT architecture , SCAN STA / SDC handling , DFT timing closure

Strong ATPG verification background, coverage improvement, simulation debug skills.

Good software and scripting skills

Ability to work in a team environment

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