DFT Lead Engineer

Job Description-

• The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these.
• The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.
• Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations, MBIST and BSCAN simulations using industry standard tools of Cadence/Siemens Tessent/Synopsys.
• He/she must have worked on zero delay as well as SDF Timing Simulations.
• Must have good debugging skills using GUI mode of industry standard simulators like VCS, NCSim or Xcelium.
• The candidate should have worked on fault models like stuck-at, Transition Delay Faults(TDF), IDDQ and should have experience in scan test coverage improvement techniques.
• He/she should have worked in SoC level DFT with experience in OCC/OPCG insertion, EDT/Compression logic insertion, clock mo...