Job Description

Required Skills and Experience:

  • DFT Engineering Manager with demonstrated hands-on experience in any areas of DFT – BIST, ATPG, Post-Silicon Debug, Boundary Scan etc. for at least 10 years
  • Manage a team of high calibre DFT engineers and have excellent customer management skills.
  • Working closely with the management to Hire talented, passionate, and high skilled DFT engineers.
  • Provide technical leadership for the DFT team by supporting all the team members on their various tasks
  • Interfacing directly with the customers (communication/reporting/technical discussions)
  • Proposing new methodologies to continuously improve the DFT flow
  • Solid knowledge & experience in defining test solutions for multi-million gate SOC (Scan & MBIST) with Mixed Signal IPs (PLL, High Speed SERDES, DDR)
  • Knowledgeable in full SOC design and manufacturing cycle with specialized/direct experience in multiple areas; RTL/Custom Logic design, Synthesis, P&R, STA, Integration, Verification, Characterization and ATE test
  • Past experience in leading the team to successful silicon bring-up and problem solving in a complex system
  • Strong planning, project, and people management skills required. Must have experience developing leads and individual contributors
  • Experienced hands-on technical manager not afraid to dig into details to provide technical direction
  • Proven track record of delivering results and meeting quality, cost, and time-to-market objectives

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