Job Description

RTL Design Engineer (ASIC)


Location: Chennai, Tamil Nadu

Experience: 1 to 3 Years


Job Description


Job Role:

  • Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog.
  • Develop micro-architecture specifications and deliver high-quality, synthesizable RTL.
  • Integrate complex subsystems into SoC environments and support design convergence.
  • Collaborate with system architects, verification, SoC, software, DFT, and physical design teams.
  • Apply low-power design techniques including clock gating, power gating, and multi-voltage domains.
  • Analyze and optimize for performance, area, and power.
  • Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges.
  • Conduct CDC and lint checks using tools...

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