Job Description
Job Description
Day‑to‑Day Responsibilities
• Take RTL from internal design teams and push it through the full frontend implementation flow (synthesis → DFT → STA → LEC → signoff).
• Implement and iterate SDC timing constraints to achieve timing closure for assigned partitions.
• Run synthesis, generate timing reports, perform quality checks, and prepare implementation data for backend teams.
• Partner with external PNR (Place & Route) vendors to resolve timing issues, DFT logic placement impacts, and integration concerns.
• Execute multiple rounds of design and timing improvements across all assigned partitions.
• Track and meet internal quality metrics for each iteration, ensuring final partitions meet foundry‑level signoff requirements ahead of December 2026 tapeout.
• Use Synopsys and Siemens tools to execute flow steps and validate results at each stag
A client of Insight Global is seeking a highly skilled ASIC Frontend Digital Implementation Engin...
Day‑to‑Day Responsibilities
• Take RTL from internal design teams and push it through the full frontend implementation flow (synthesis → DFT → STA → LEC → signoff).
• Implement and iterate SDC timing constraints to achieve timing closure for assigned partitions.
• Run synthesis, generate timing reports, perform quality checks, and prepare implementation data for backend teams.
• Partner with external PNR (Place & Route) vendors to resolve timing issues, DFT logic placement impacts, and integration concerns.
• Execute multiple rounds of design and timing improvements across all assigned partitions.
• Track and meet internal quality metrics for each iteration, ensuring final partitions meet foundry‑level signoff requirements ahead of December 2026 tapeout.
• Use Synopsys and Siemens tools to execute flow steps and validate results at each stag
A client of Insight Global is seeking a highly skilled ASIC Frontend Digital Implementation Engin...
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