Job Description
Client Background & Position Overview
Our client is a globally recognized technology leader investing heavily in next-generation semiconductor R&D. Their European research center, located in the heart of Leuven’s innovation ecosystem, focuses on advanced chip architecture and integration solutions to support future computing and communication systems.
As part of their expanding initiative in 3DIC development, the team is seeking a highly skilled Design for Test (DFT) Engineer to lead research and implementation of cutting-edge test strategies for complex semiconductor architectures including 3DIC, memory, and analog IP.
Responsibilities
Develop and refine DFT methodologies for digital logic chips, focusing on defect mechanisms, fault simulation, and failure diagnostics.
Design and validate testing strategies for 3DIC chips, including defect modeling and interconnect reliability analysis.
C...
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