Job Description

Role : Emulation Engineer

Location : Hyderabad

Preferred : Immediate to 30 days

Experience : 4-5 yeats

  • Experience in emulation/prototyping using Cadence/Synopsys tool flows (Palladium/Protium/HAPS/Zebu)
  • Working knowledge of System Verilog & Verilog language semantics and compilation flows
  • Solid understanding on SOC architecture and AXI protocol
  • Good communication skills and team collaboration


Interested can apply below or share cvs to [email protected]

Apply for this Position

Ready to join ACL Digital? Click the button below to submit your application.

Submit Application