ENGR PRIN, DESIGN LAYOUT; DSGN

ROLE

•Be the innovation lead for the analog layout automation and optimization engine •Build the POC to auto-layout the first EoPM design. •Own the definition of constraints required for different EoPM design layouts •Collaborate with System Designers and CAD teams for automation #L1-LK1 •10-12 years of experience in analog layout using Cadence Virtuoso. •Experience with 2.5D and 3D interposer layout considerations •Experience with automation and optimization of layout •Excellent understanding of Analog Layout concepts (. Matching, Electro- migration, Latch-up, Coupling, Cross-talk, IR-drop, Active and Passive parasitic devices etc. •Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout. •Work closely with the verification team to address layout-related issues and ensure design robustness. •Follow design rules, guidelines, and best practices to ensure design manufacturability and yield. •Collaborate with process engineers to understand process requirements and optimize layout designs accordingly. •Conduct layout parasitic extraction and work with the simulation team to validate and optimize design performance. •Participate in design reviews and contribute to overall design improvements. •Document designs, processes, and testing procedures •Stay updated with the latest advancements in analog layout techniques, process technologies, and industry standards. #L1-LK1

Bachelors degree with 10 to 12 yrs of experience in analog layout using Cadence Virtuoso.

#L1-LK1