Job Description
Role : FPGA Prototyping Engineer
Experience : 5-6 years
Preferred : immediate to 30 days notice
Location : Hyderabad.
FPGA design & prototyping using Cadence/Synopsys/Vivado flows.
Strong RTL(verilog/system verilog) skills with experience in IP development.
Ability to verify designs by writing simple testbenches.
Strong foundation in logic synthesis and timing closure concepts.
Good knowledge of SoC architecture, AXI bus protocols, hardware debug.
Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus.
Interested can apply here or share cvs to [email protected]
Experience : 5-6 years
Preferred : immediate to 30 days notice
Location : Hyderabad.
FPGA design & prototyping using Cadence/Synopsys/Vivado flows.
Strong RTL(verilog/system verilog) skills with experience in IP development.
Ability to verify designs by writing simple testbenches.
Strong foundation in logic synthesis and timing closure concepts.
Good knowledge of SoC architecture, AXI bus protocols, hardware debug.
Experience of working with Xilinx FPGAs, Vivado tool flows and micro architecture development is a plus.
Interested can apply here or share cvs to [email protected]
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