Job Description
Minimum Qualification:
Bachelor's/ Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
3-10 years of experience with formal verification ASIC design.
Experience writing formal properties using System Verilog Assertions (SVA).
Experience with...
Bachelor's/ Master's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
3-10 years of experience with formal verification ASIC design.
Experience writing formal properties using System Verilog Assertions (SVA).
Experience with...
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