Formal Verification Engineer

Job Title: Formal Verification Engineer

Location: Hyderabad

Experience: 5+ Years

Notice Period: Immediate to 15 Days

We are seeking a Senior Formal Verification Engineer with 5+ years of ASIC/SoC verification experience. The role involves property checking, assertion-based verification (SVA), equivalence checking, and CDC/RDC validation using tools like JasperGold, VC Formal, or Questa Formal. Strong expertise in SystemVerilog, RTL debugging, and formal methodologies is required. Candidates should have solid understanding of digital design concepts and low-power verification (UPF/CPF is a plus). Excellent debugging and problem-solving skills are essential. Immediate joiners or candidates with a notice period up to 15 days are preferred.

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